The Simple Differential OTA

Design

Christian Enz

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

Initialization

Introduction

Schematic of the simple differential OTA.

This notebook presents the design of the simple differential OTA shown in the above figure. The OTA is analyzed in details in the Analysis Notebook, leading to all the design equations that are then used in this Notebook to size all transistors and set the bias currents in order to achiev a give set of specifications

We will design the circuit with M1a-M1b in a separate well for the specifications given below. In this example, we don't give any specification on the slew-rate. However the sew-rate specification can determine a bias current that is way above the one derived in this example ignoring the SR. If the SR is too high, we can move to adaptive biasing OTAs.

Process Parameters

All the parameters required for the design are given below. They correspond to a generic $0.18\,\mu m$ process.

Main physical parameters:
═════════════════════════
$T =$ 300 K
$U_T =$ 25.875 mV 
Main process parameters for TSMC 0.18um:
════════════════════════════════════════
$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm 
nNMOS parameters:
═════════════════
Long-channel sEKV parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$ 
Overlap capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$ 
Junction capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$ 
1/f noise parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$ 
Matching parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$ 
Source and drain sheet resistance:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$ 
Channel width and length corrections
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$\Delta W =$ 39 nm
$\Delta L =$ −76 nm 
pNMOS parameters:
═════════════════
Long-channel sEKV parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$ 
Overlap capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$ 
Junction capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$ 
1/f noise parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$ 
Matching parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$ 
Source and drain sheet resistance:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$ 
Channel width and length corrections
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

OTA Specifications

$A_{dc} =$ 60 dB
$GBW =$ 1 MHz
$C_L =$ 1 pF
$V_{os,max} =$ 10.0 mV

Design procedure

Sizing M1a-M1b

M1a-M1b are biased in weak inversion in order to minimize the input-referred offset. They are sized according to the specification on the GBW and the load capacitance and the required slew-rate.

Recalling that \begin{equation*} GBW = \frac{G_{m1}}{2 \pi C_{out}}, \end{equation*} where $C_{out}$ is the total output capacitance which includes the parasitic capacitance and the load capacitance $C_L$. Since we do not yet know the sizes of M1a-M2b, we can not estimate the total output capacitance. We will start assuming $C_{out}=C_L$.

$G_{m1}$ is the gate transconductance of M1a-M1b which in weak inversion is given by \begin{equation*}\ G_{m1} = \frac{I_b}{n U_T}. \end{equation*} The bias current $I_b$ is the current flowing in each transistor M1a-M1b when the input differential voltage is zero. The bias current provided by M3b is therefore $2 I_b$. The bias current must satisfy the following inequality: \begin{equation*} I_b \geq 2\pi n_{0n} U_T C_L GBW_{min}. \end{equation*} which for the given specifications gives

$I_{bmin} =$ 206.7 nA

The corresponding slew-rate is given by

$SR_{min} =$ 206.7 kV/s

which we will consider as sufficient. If this is not the case, the bias current $I_b$ should be increased or a dynamic or adaptive biasing OTA should be used. To have some margin to account for the additional parasitic capacitance at the output due to the junction capacitances and that add to the load capacitance $C_L$, we set $I_b$ to

$I_b =$ 250 nA

and the inversion coefficient $IC$ to

$IC_1 =$ 0.1

The transconductance can be calculated from the $G_m/I_D$ function as:

$G_{m1} =$ 6.962 µA/V

which leads to the following $GBW$

$GBW =$ 1.1 MHz

which is slightly higher than the target specification offering some margin.

Knowing the drain current $I_{D1}$ and the inversion coefficient, we can calculate the $W/L$ aspect ratio for M1a-M1b as

$\frac{W_1}{L_1} =$ 3.5

The degree of freedom left ($W_1$ or $L_1$) can be determined by constraints either on the DC gain, the offset voltage or the flicker noise. In this example we will set a minimum DC gain. The latter is given by \begin{equation*} A_{dc} =\frac{G_{m1}}{G_o} \end{equation*} where $G_o = G_{ds1b} + G_{ds2b}$ is the conductance to the AC ground at the output node. The output conductances are estimated with the following simple model \begin{equation*} G_{dsi} = \frac{I_{Di}}{V_{Mi}} \end{equation*} with $V_{Mi} = \lambda_i \cdot L_i$. Note that this model of the output conductance is only a very rough approximation and that the gain should be checked by simulation. Some margin can be taken to ensure a sufficient DC gain.

A good optimum for the output conductance is to set $G_{ds1b}=G_{ds2b}$ or since M1a-M2b share the same bias current $V_{M1b} = V_{M2b}$. The minimum length of M1a-M2b is then given by

$L_1 =$ 3.591 µm

which we round to

$L_1 =$ 3.6 µm

which gives the width of M1a-M1b

$W_1 =$ 12.587 µm

which we round to

$W_1 =$ 12.6 µm

We can recompute the transconductance and gain-bandwidth product for the chosen dimensions of M1a-M1b

$I_{spec1} =$ 2.5 µA
$IC_1 =$ 0.1
$G_{m1} =$ 6.962 µA/V
$GBW =$ 1.1 MHz

Sizing M2a-M2b

The gate voltage of M2a should be set as low as possible for a given maximum common mode input voltage still keeping M1a in saturation. For a maximum input common-mode voltage $V_{ic,max}$ given by

$V_{icmax} =$ 1 V

The minimum source-to-gate voltage of M2a $V_{SG2a}$ for this maximum input common mode voltage $V_{ic,max}$ is given by \begin{equation*} V_{SG2a} = V_{DD} - V_{icmax} + V_{GS1a} - V_{DSsat1a}. \end{equation*} The gate-to-source voltage $V_{GS1a}$ and the saturation voltage $V_{DSsat1a}$ of M1a-M1b are given by

$V_{GS1} =$ 382.361 mV
$V_{DSsat1} =$ 104.784 mV
$V_{SG2} =$ 977.576 mV

We set $V_{SG2}$ to

$V_{SG2} =$ 900.0 mV

This corresponds to an inversion coefficient given by

$IC_2 =$ 41.320

We choose

$IC_2 =$ 40

The saturation voltage of M2a-M2b is then given by

$V_{DSsat2} =$ 343 mV

The specific current $I_{spec}$, transconductance $G_m$ and $W/L$ are then given by

$I_{spec2} =$ 6.2 nA
$G_{m2} =$ 1.1 µA/V
$\frac{W_2}{L_2} =$ 3.6e-02

The length of M2a-M2b is set by the dc gain similarly to the length of M1a-M1b

$L_2 =$ 3.600 µm

We keep

$L_2 =$ 3.6 µm

We can now derive M2a-M2b transistor width

$W_2 =$ 130.0 nm

which is smaller than the minimum width $W_{min}$. We then set $W_2$ to the minimum width and deduce the length

$W_2 =$ 200 nm
$L_2 =$ 5.540 µm

which we round to

$L_2 =$ 5.54 µm

Since $L_2$ is longer than the initial value it will not affect the DC gain which should actually be slightly larger. We can evaluate the transconductance $G_{m2}$

$IC_2 =$ 40.0
$G_{m2} =$ 1.1 µA/V

Since $G_{m2}$ may become small, we need to check whether the non-dominant pole $f_{p2}$ lies sufficiently highabove the GBW to insure the desired phase margin. The non-dominant pole is given \begin{equation*} \omega_{p2} = \frac{G_{m2}}{C_2}, \end{equation*} where $C_2$ is given by \begin{equation*} C_2 = 2(C_{GS2} + C_{GB2}) \end{equation*} Assuming M2 is in strong inversion and saturation, we have \begin{equation*} C_{GS2} \cong \frac{2}{3}\,W_2\,L_2\,C_{ox} + W_2 \cdot C_{GSOp} \end{equation*} and \begin{equation*} C_{GB2} \cong \frac{n_{0p}-1}{3\,n_{0p}}\,W_2\,L_2\,C_{ox} + W_2 \cdot C_{GBOp}. \end{equation*}

The capacitance at node 2 scales with $W_2$ and $L_2$ according to \begin{equation*} C_2 = W_2\,L_2 \cdot C_{WL} + W_2 \cdot C_W, \end{equation*} with \begin{align*} C_{WL} &= 2\,C_{ox} \left(\frac{2}{3} +\frac{n_{0p}-1}{3\,n_{0p}}\right),\\ C_W &= 2(C_{GSop} + G_{GBop}). \end{align*}

$C_{GS2} =$ 5.780 fF
$C_{GB2} =$ 853.014 aF
$C_2 =$ 13.266 fF
$f_{p2} =$ 12.968 MHz

which is sufficient.

In case it would not be, we then need to reduce $IC_2$ which will increase the $G_m/I_D$ and since the current is set by the bias current $I_b$, it will increase $G_{m2}$. If $W_2$ is set to its minimum value $W_{min}$, decreasing $IC_2$ keeping the same current, will increase the $W_2/L_2$. With $W_2$ set, this leads to a decrease of $L_2$ and hence a decrease of $C_2$. The increase of $G_{m2}$ an decrease of $C_2$ leads to an increase of $f_{p2}$, as required.

Therefore, if $f_{p2}$ is not suffciently higher than $GBW$, we can use the following script to find the required $IC$ for having the non-dominant pole at 10 times the $GBW$.

$IC_2 =$ 45.943
$G_{m2} =$ 1.014 µA/V
$G_{m1}/G_{m2} =$ 6.867
$\frac{W_2}{L_2} =$ 3.1e-02
$W_2 =$ 200.000 nm
$L_2 =$ 6.363 µm
$C_2 =$ 16.136 fF
$f_{p2} =$ 10.000 MHz
$f_{p2}/GBW =$ 10

We see that $IC_2$ has been lowered, increasing $G_{m2}$ and $W_2/L_2$ for the given current $I_b$. Since $W_2$ hits $W_{min}$, the length $L_2$ has been decreased, reducing $C_2$ at the same time to keep $f_{p2}$ at 10 times the GBW.

We finally choose

$W_2 =$ 200.00 nm
$L_2 =$ 6.30 µm

Sizing M3a-M3b

We now need to size M3a-M3b according to the minimum common mode input voltage $V_{ic,min}$ to be handled

$V_{icmin} =$ 800 mV

which leads to the saturation voltage of M3b

$V_{GS1} =$ 382.4 mV
$V_{DSsat3} =$ 417.6 mV

We can derive the corresponding inversion coefficient $IC_3$ directly from the normalized saturation voltage

$IC_3 =$ 61.130

from which we get the $W/L$ ratio

$\frac{W_3}{L_3} =$ 1.144e-02

We need to set $W_3$ to $W_{min}$ and recalculate the length $L_3$

$W_3 =$ 200 nm
$L_3 =$ 17.483 µm

which we round to

$L_3 =$ 17.5 µm

Summary

We will summarize the result of the sizing procedure and save all the information in a dataframe and write it to an excel sheet.

$I_b =$ 250 nA
$W_{1a} =$ 12.6 µm, $L_{1a} =$ 3.6 µm
$W_{1b} =$ 12.6 µm, $L_{1b} =$ 3.6 µm
$W_{2a} =$ 200.0 nm, $L_{2a} =$ 6.3 µm
$W_{2b} =$ 200.0 nm, $L_{2b} =$ 6.3 µm
$W_{3a} =$ 200.0 nm, $L_{3a} =$ 17.5 µm
$W_{3a} =$ 200.0 nm, $L_{3a} =$ 17.5 µm

Specifications

The specifications are recalled below.

Name Value
0 AdcdB 6.000000e+01
1 GBWmin 1.000000e+06
2 CL 1.000000e-12
3 Vosmax 1.000000e-02
4 PMdeg 6.000000e+01

Bias

The bias information are summarized below.

Name Value
0 VDD 1.800000e+00
1 Ib 2.500000e-07

Transistor sizes

The transistor sizes are summarized below.

Type Function W L ID W/L Ispec IC VP-VS VG-VT0 ... CGSe CGDe CGBe CBSe CBDe CGS CGD CGB CBS CBD
M1a n DP 1.26E-05 3.60E-06 2.50E-07 3.50E+00 2.50E-06 9.99E-02 -5.71E-02 -4.49E-02 ... 4.62E-15 4.62E-15 0.00E+00 5.18E-14 5.18E-14 3.58E-14 4.62E-15 7.51E-14 6.03E-14 5.18E-14
M1b n DP 1.26E-05 3.60E-06 2.50E-07 3.50E+00 2.50E-06 9.99E-02 -5.71E-02 -4.49E-02 ... 4.62E-15 4.62E-15 0.00E+00 5.18E-14 5.18E-14 3.58E-14 4.62E-15 7.51E-14 6.03E-14 5.18E-14
M2a p CM 2.00E-07 6.30E-06 2.50E-07 3.17E-02 5.50E-09 4.55E+01 3.72E-01 2.85E-01 ... 6.57E-17 6.57E-17 0.00E+00 4.64E-15 4.64E-15 6.60E-15 6.57E-17 9.61E-16 6.64E-15 4.64E-15
M2b p CM 2.00E-07 6.30E-06 2.50E-07 3.17E-02 5.50E-09 4.55E+01 3.72E-01 2.85E-01 ... 6.57E-17 6.57E-17 0.00E+00 4.64E-15 4.64E-15 6.60E-15 6.57E-17 9.61E-16 6.64E-15 4.64E-15
M3a n CM 2.00E-07 1.75E-05 5.00E-07 1.14E-02 8.17E-09 6.12E+01 4.31E-01 3.39E-01 ... 7.33E-17 7.33E-17 0.00E+00 1.06E-14 1.06E-14 1.84E-14 7.33E-17 2.38E-15 1.56E-14 1.06E-14
M3b n CM 2.00E-07 1.75E-05 5.00E-07 1.14E-02 8.17E-09 6.12E+01 4.31E-01 3.39E-01 ... 7.33E-17 7.33E-17 0.00E+00 1.06E-14 1.06E-14 1.84E-14 7.33E-17 2.38E-15 1.56E-14 1.06E-14

6 rows × 33 columns

OTA Characteristics

In this section, we read the results of the sizing procedure from the Excel file without having to go through it again and check whether the specs are achieved. We need to run the first intialization before starting the notebook at this point.

Sizing summary

Process parameters

Main physical parameters:
═════════════════════════
$T =$ 300 K
$U_T =$ 25.875 mV 
Main process parameters for TSMC 0.18um:
════════════════════════════════════════
$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm 
nNMOS parameters:
═════════════════
Long-channel sEKV parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$ 
Overlap capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$ 
Junction capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$ 
1/f noise parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$ 
Matching parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$ 
Source and drain sheet resistance:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$ 
Channel width and length corrections
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$\Delta W =$ 39 nm
$\Delta L =$ −76 nm 
pNMOS parameters:
═════════════════
Long-channel sEKV parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$ 
Overlap capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$ 
Junction capacitances:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$ 
1/f noise parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$ 
Matching parameters:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$ 
Source and drain sheet resistance:
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$ 
Channel width and length corrections
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

Specifications

Value
Name
AdcdB 6.00E+01
GBWmin 1.00E+06
CL 1.00E-12
Vosmax 1.00E-02
PMdeg 6.00E+01
$A_{dc} =$ 60 dB
$GBW =$ 1 MHz
$V_{osmax} =$ 10 mV
$PM =$ 60 deg

Bias information

Value
Name
VDD 1.80E+00
Ib 2.50E-07
$I_b =$ 250 nA

Transistors information

Type Function W L ID W/L Ispec IC VP-VS VG-VT0 ... CGSe CGDe CGBe CBSe CBDe CGS CGD CGB CBS CBD
M1a n DP 1.26E-05 3.60E-06 2.50E-07 3.50E+00 2.50E-06 9.99E-02 -5.71E-02 -4.49E-02 ... 4.62E-15 4.62E-15 0 5.18E-14 5.18E-14 3.58E-14 4.62E-15 7.51E-14 6.03E-14 5.18E-14
M1b n DP 1.26E-05 3.60E-06 2.50E-07 3.50E+00 2.50E-06 9.99E-02 -5.71E-02 -4.49E-02 ... 4.62E-15 4.62E-15 0 5.18E-14 5.18E-14 3.58E-14 4.62E-15 7.51E-14 6.03E-14 5.18E-14
M2a p CM 2.00E-07 6.30E-06 2.50E-07 3.17E-02 5.50E-09 4.55E+01 3.72E-01 2.85E-01 ... 6.57E-17 6.57E-17 0 4.64E-15 4.64E-15 6.60E-15 6.57E-17 9.61E-16 6.64E-15 4.64E-15
M2b p CM 2.00E-07 6.30E-06 2.50E-07 3.17E-02 5.50E-09 4.55E+01 3.72E-01 2.85E-01 ... 6.57E-17 6.57E-17 0 4.64E-15 4.64E-15 6.60E-15 6.57E-17 9.61E-16 6.64E-15 4.64E-15
M3a n CM 2.00E-07 1.75E-05 5.00E-07 1.14E-02 8.17E-09 6.12E+01 4.31E-01 3.39E-01 ... 7.33E-17 7.33E-17 0 1.06E-14 1.06E-14 1.84E-14 7.33E-17 2.38E-15 1.56E-14 1.06E-14
M3b n CM 2.00E-07 1.75E-05 5.00E-07 1.14E-02 8.17E-09 6.12E+01 4.31E-01 3.39E-01 ... 7.33E-17 7.33E-17 0 1.06E-14 1.06E-14 1.84E-14 7.33E-17 2.38E-15 1.56E-14 1.06E-14

6 rows × 33 columns

Open-loop gain

$A_{dc} =$ 62.117 dB
$G_{m1} =$ 6.962 µA/V
$G_{m2} =$ 1.019 µA/V
$f_0 =$ 868.405 Hz
$GBW =$ 1.108 MHz
$f_{p2} =$ 10.717 MHz
$f_{z2} =$ 21.435 MHz

The $GBW$ given above is only an estimation. We can find the actual $GBW$ accounting for the non-dominant pole using the following script.

$GBW =$ 1.000 MHz (from specifications)
$GBW = \frac{G_{m1}}{C_o} =$ 1.108 MHz (estimation neglecting the effect of the zero)
$GBW = $ 1.104 MHz (estimation including effect of the zero)
$f_0 =$ 868.405 Hz (dominant pole)
$f_{p2} =$ 10.717 MHz (non-dominant pole)

In this case the actual $GBW$ is very close to the estimated one.

We can plot the magnitude and phase of the open-loop gain.

PGBW = −92.887 deg
PM = 87.113 deg

Input-referred noise

We can now calculate the noise excess factor of the OTA and the input-referred thermal noise resistance.

$G_{m1} =$ 6.962 µA/V
$G_{m2} =$ 1.019 µA/V
$G_{m1}/G_{m2} =$ 6.835
$\gamma_{n1} =$ 0.653
$\gamma_{n2} =$ 0.841
$\eta_{th} =$ 0.188
$R_{nt} =$ 223 kOhm
$\gamma_{ota} =$ 1.553
$\sqrt{S_{ninth}} =$ 60.774 $\frac{nV}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninth}) =$ -144.326 $\frac{dBv}{\sqrt{Hz}}$

We see that the OTA thermal noise excess factor is only slightly larger than that of the differential pair. This is due to the rather large $G_{m1}/G_{m2}$ ratio.

We can now compute the input-referred flicker noise and the corner frequency.

$(G_{m1}/G_{m2})^2 =$ 46.7
$\rho_p/\rho_n =$ 8.3
$\frac{W_1 \cdot L_1}{W_2 \cdot L_2} =$ 36.0
$\eta_{fl} =$ 6.421
$\sqrt{S_{ninfl}(1\,Hz)} =$ 17.718 $\frac{\mu V}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninfl}(1\,Hz)) =$ -95.032 $\frac{dBv}{\sqrt{Hz}}$
$f_k =$ 85.0 kHz

We can plot the input-reffered noise

Input-referred offset

The variance of the input-referred offset is given by \begin{equation*} \sigma_{V_{os}}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \left(\sigma_{\beta_1}^2 + \sigma_{\beta_2}^2\right) + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \sigma_{V_{T02}}^2 + \sigma_{V_{T01}}^2, \end{equation*} where \begin{align} \sigma_{\beta_i}^2 &= \frac{A_{\beta}^2}{W_i L_i} \qquad i=1,2,\\ \sigma_{V_{T0i}}^2 &= \frac{A_{VT}^2}{W_i L_i} \qquad i=1,2. \end{align} From the values calculated above we get

$\sigma_{\beta1} =$ 1.485 m
$\sigma_{\beta2} =$ 8.909 m
$\sigma_{VT1} =$ 742.392 µV
$\sigma_{VT2} =$ 4.454 mV
$\sigma_{Vos} =$ 1.040 mV

Conclusion

This notebook showed how to design the simple OTA from given specifications using the design equations derived in the Analysis Notebook. The result of the design has been checked. The next step is to validate the design by simulations. This is done in the Verification Notebook.